Field of the Invention
The invention relates to a redundant circuit configuration for an integrated semiconductor memory as is disclosed, for instance, in the IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, January 1991, page 12 ff., or in European Patent Application 0 472 209 A2, especially for the repair of word lines or bit lines in dynamic memories (DRAMs).
As raster dimensions become smaller with each new generation of memories, the vulnerability to defects in the cell field rises. Profitable production therefore requires devices on the memory with which such defects can be repaired. As a rule, redundant cells are provided, which are inserted in place of defective cells through the use of programmable coding elements.
In large-capacity memories, the memory cells are subdivided into a plurality of blocks. Due to the matrix-like configuration of memory cells, the redundant cells must likewise be disposed in rows and columns. Those redundant lines are generally constructed at the edge of the cell fields. They are each selected through the use of a programmable address circuit in conjunction with the addresses being applied.
By way of example, such programmable address circuits can be laser-separable fuse blocks. Typically, one or more lines is permanently assigned to each fuse block. In general, as many fuse blocks and address comparators will be used as there are independent memory blocks.
A typical prior art circuit for coding a column address in the case of column redundance is described below with regard to FIG. 1. The disadvantages thereof are that transverse currents may occur twice in each memory block group and there is an overly high number of lines and an attendant unfavorably large output gate. The disadvantages of the redundant address decoder are that it requires a large amount of space and can therefore result in a reduction in the number of chips per wafer, and the required surface area for fuse blocks together with trigger circuits is approximately twice as large as an area occupied by the redundant memory cells. Additionally, such a circuit leads to high current consumption, especially with column redundance, where the triggering of the column redundance is operationally ready over the entire active cycle. It also places a severe strain on output lines.
In European Patent Application 0 492 099 A2, a redundant circuit configuration is described where the internal block addresses of the columns or rows to be replaced are programmed in fuse blocks and only as many separable connections as in the bit width are needed. The addresses are written by a local bus to the associated redundant decoders in the on-state phase of the memory. In the redundant decoders, the addresses of the columns or rows to be replaced are stored in memory by flip-flop circuits. The comparison between the applied address and the addresses of the columns and rows to be replaced is carried out separately in each redundant decoder. Accordingly, while a savings is attained in terms of the number of separable connections, the current consumption remains high.